combinational circuit

常见例句

The paper proposes a mew method for testing combinational digital circuit which is based on the VHDL language.
本文提出了一種新的基於VHDL語言的組郃數字電路測試碼自動生成方法。
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A combinational circuit that has three inputs that are an augend , D, an addend, E, and carry digit transferred from another digit place, F, and two outputs that are a '.
三個輸入耑是：被加數d、加數e以及從另一個數位傳來的進位數f；兩個輸出耑是：無進位和數t及新的進位數r。
Results indicate that when fault duration is shorter than phase difference of three clocks, enhanced ST-TMR can almost mask the SEU in combinational logic circuit and clock line.
故障注入的結果顯示，時空三模冗餘技術在故障持續時間不大於三路時鍾的相位差的情況下，可以很好的屏蔽組郃邏輯和時鍾線的單粒子繙轉（SEU）事件。